The New Topology of Multilevel Inverter with Less Number of Switches

Authors

  • Thottempudi Prasanth UG Student Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
  • Garikapati Siva Sankar UG Student Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
  • Bathula Swarna Babu UG Student Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
  • Dupati Gopi UG Student Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
  • Chandana Gowtham Sai UG Student Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
  • G V K Murthy Professor, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
  • K Sowjan kumar Assistant Professor, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
  • K Naresh Assistant Professor, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
  • S Kavitha Assistant Professor, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author

Keywords:

Multilevel Inverter, Switches, DCMLI, FCMLI, CHBMLI, Thottempudi Prasanth

Abstract

A new multilayer inverter topology is  proposed in this study. The cascaded feature is used in this  innovative topology. In addition to the isolated DC sources  seen in Cascaded H- bridge. The clamping diode in Diode  and the multilevel inverter (CHB-MLI) Inverter with  Clamped Multilevel (DC-MLI). With these advantages, an  inverter topology with 18 total component counts when  coupled had been discovered. This proposed topology has  the potential to generate up to According to the ratio  allocated to its DC sources, there are 17 output levels.  Aside from increasing the number of output voltage levels,  this study has a relatively low number of component  counts. The THD limit defined by IEEE standard is also a  goal (i.e. 5 percent) all voltage applications under 69kV.  To ensure that the suggested topology is functional, it is  being simulated in Mat lab/Simulink with various  modulation indexes. The amount of THD, the number of  voltage outputs, and the RMS voltage are all being  monitored and discussed. Finally, to assess the uniqueness  of the suggested topology, a comparison study with  recently disclosed topologies is being carried out. 

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References

M. H. Mondol, P. B. Shuvra, M. K. Hosain, F. Samad, and M. W. Rahman, “A Novel Single Phase Multilevel Inverter Topology with Reduced Number of Switching Elements and Optimum THD Performance,” in 2019 International Conference of Electrical, Computer and Communication Engineering (ECCE), Feb. 2019.

K. H. Law, M. S. A. Dahidah, and N. Mariun, “Cascaded multilevel inverter based statcom with power factor correction feature,” in 2011 IEEE Conf. Sustain. Utilization and Develop. in Eng. And Technol., Dec. 2011, pp. 12-18.

K. H. Law, M. S. A. Dahidah, G. S. Konstantinou, and V. G. Agelidis, “SHE-PWM cascaded multilevel converter with adjustable DC sources control for STATCOM applications,” in 7th Int. Power Electron. And Motion Cont. Conf., Aug. 2012, pp. 330-334

. [4] K. H. Law and M. S. A. Dahidah, “DC-DC boost converter based MSHE-PWM cascaded multilevel inverter control for STATCOM systems,” in 2014 Int. Power Electron. Conf., Aug. 2014, pp. 1283- 1290.

K. H. Law and M. S. A. Dahidah, “New current control algorithm incorporating multilevel SHE-PWM approach for STATCOM operation under unbalanced condition,” in 2014 IEEE 5th Int. Symp. Power Electron. for Distrib. Generation Syst., Aug. 2014, pp. 1-7.

K. H. Law, W. P. Q. Ng, and W. K. Wong, "Flyback cascaded multilevel inverter based SHE-PWM control for STATCOM applications," Int. J. Power Electron. Drive Syst., vol. 8, no. 1, pp. 100- 108, 2017.

K. H. Law, “An Effective Voltage Controller for Quasi-Z Source Inverter-Based STATCOM with Constant DC-Link Voltage," IEEE Trans. Power Electron., vol. 33, iss. 9, pp. 8137-8150, Sep. 2018.

K. H. Law and W. P. Q. Ng, "Dual Closed-Loop Scheme with Lead Compensator and Proportional Controller for Quasi Z-Source Inverter Based STATCOM," in 2018 IEEE 7th Int. Conf. Power Energy, Apr. 2019, pp. 56-61.

K. H. Law, W. P. Q. Ng, and P. I. Au, “Design, Modelling and Control Implementation of PV-MPPT Based DC-DC Converter for STATCOM,” IOP Conference Series: Materials Science and Engineering, vol. 495, no. 1, pp. 1-11, 2019.

K. H. Law, W. P. Q. Ng, and K. I. Wong, “Active Harmonic Filtering Using Multilevel H-bridge Inverter Based STATCOM,” IOP Conference Series: Materials Science and Engineering, vol. 495, no. 1, pp. 1-9, 2019.

F. Blaabjerg, Z. Chen, and S. B., Kjaer, “Power Electronics as efficient interface in dispersed power generation systems,” IEEE Transactions on Power Electronics, vol. 19, issue, 5, pp. 1184-1194, Sept. 2004.

S. Rohner, S. Bernet, M. Hiler, and R. Sommer, “Modulation, Losses, And Semiconductor Requirements of Modular Multilevel Converter,” IEEE Transactions on Industrial Electronics, vol. 57, no. 8, pp. 2633- 2642, Aug. 2010.

J. Amini and A. Abedini, “A Straightforward Closed-Loop Control Strategy for A Single Phase Assymemetrical Flying Capacitor Multilevel Inverter,” in 4th Power Electronics, Drive Systems & Technologies Conference, Feb. 2013.

S.Ponkumar, S. M. Rivera, F. Kamroon, and S. G. Kumar, “Realization of Cascaded Multilevel Inverter” in CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies, Oct. 2017.

M. A. Hoddrizadeh, M. Sarbanzadeh, M. Rivera, J. Munoz, A. Villalon, and C. Munoz, “New Single-Phase Asymmetric Reduced Multilevel Inverter Based on Switched-Diode for Cacaded Multilevel Inverters,” in IEEE International Conference of Industrial Technology, Feb. 2019.

T. Muhammad, A. U. Khan, H. Jan, M. Y. Usman, J. Javid, A. Aslam, “Cascaded Symmetric Multilevel Inverter with Reduced Number of Controlled Switches.” International Journal of Power Electronics and Drive System, vol. 8, no. 2, pp. 795-803, June 2017.

D. Cui, Q. Ge, Z. Zhou, and B. Yang, “A Closed-Loop Voltage Balance Method for Five- Level Diode Clamped Inverter,” 43rd Annual Conference of the IEEE Industrial Electronics Society, Nov. 2017.

G. S. Lakshmi, “Five-Level and Seven-Level DCMI fed to IPMSM,” International Conference on Electrical Engineering Research & Practice, Nov. 2019.

S. Choudhury, S. Nayak, T. B. Dash, and P. K. R. Out,“A Comparative Analysis of Five Level Diode Clamped and Cascaded H-bridge Multilevel Inverter for Harmonics Reduction,” Technologies for Smart City Energy Security and Power, Mar. 2018.

M. Zolfaghar, E. Najafi, S. Hasanzadeh, “A Modified Diode Clamped with Reduced Number of Switches,” 9th Annual Power Electronics, Drives Systems and Technologies Conference, Apr. 2018.

S. T. Meraj, A. Ahmed, K. H. Law, A. Arif, and A. Masaoud, “DSP Based Implementation of SHE-PWM for Cross Switched Multilevel Inverter,” in 2019 IEEE 15th Int. Colloquium Signal Process. Its Appl., Apr. 2019, pp. 54-59.

S. T. Meraj, K. H. Law, and A. Masaoud, “Simplified Sinusoidal Pulse Width Modulation of Cross-switched Multilevel Inverter,” in 2019 IEEE 15th Int. Colloquium Signal Process. Its Appl., Apr. 2019, pp. 1- 6. 2020 11th IEEE Control and System Graduate Research Colloquium (ICSGRC 2020), 8 August 2020, Shah Alam, Malaysia

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Published

2021-09-30

Issue

Vol. 9 No. 5 (2021): International Journal of Innovative Research in Computer Science and Technology (Sep) 2021

Section

Articles

How to Cite

The New Topology of Multilevel Inverter with Less Number of Switches . (2021). International Journal of Innovative Research in Computer Science & Technology, 9(5), 128–133. Retrieved from https://acspublisher.com/journals/index.php/ijircst/article/view/11335