Design and Performance Analysis of Logic Circuits using FinFET Technology
Keywords:
FinFET, MOSFET, GDI, Shortchannel Effects, Power Consumption, Power- Delay ProductAbstract
As the dimensions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) decreases, the short channel effect (SCE) becomes a dominating concern in VLSI. The Short channel effect causes an exponential increase in the leakage current. To reduce the SCE and hence leakage current, a new technology has been developed in recent years. In this recent technology a 3D multiple gate MOSFETslike FinFET (Fin Field Effect
Transistor) has been developed which possess numerous advantages over conventional MOSFETs and has attracted many engineers anddesigners. FinFET is the new growing technology that works in the nm range to minimize short channel effects. Many companies (like Intel) have started using FinFET technology. This document is a review paper of current research on FinFET technology and discusses how it can be used in future to design new logic devices (like Adder, Comparator, MUX and De-MUX etc.) and memory devices. Various parameters of FinFET like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software (HSpice) were used to simulate power, delay, power delay product, average power dissipation and energy delay product. Thus, FinFET technology was designed to eliminatethe problem of SCE by permitting transistors to be scaled down into sub 20nm range.
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