The New Topology of Multi Level Inverter with Minimum of  Switches

K  Naresh; T Prasanth; C Gowtham Sai; D Gopi; B Swarn Babu; K Sowjan Kumar; G V K Murthy; T Ramaiah

doi:10.55524/

Authors

K Naresh Assistant Professor, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
T Prasanth B. Tech Scholar, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
C Gowtham Sai B. Tech Scholar, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
D Gopi B. Tech Scholar, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
B Swarn Babu B. Tech Scholar, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
K Sowjan Kumar B. Tech Scholar, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
G V K Murthy Professor, Department of Electrical and Electronics Engineering PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author
T Ramaiah Assistant Professor, Department of Electrical and Electronics Engineering, PACE Institute of Technology and Sciences, Ongole, Andhra Pradesh, India Author

DOI:

https://doi.org/10.55524/

Keywords:

Topology, THD, multi-level Inverter, DC

Abstract

A new multilayer inverter topology is proposed in this study. The cascaded feature is used in this innovative topology. In addition to the isolated DC sources seen in Cascaded H-bridge. The clamping diode in Diode and the multilevel inverter (CHB-MLI) Inverter with Clamped Multilevel (DC-MLI). With these advantages, an inverter topology with 18 total component counts when coupled had been discovered. This proposed topology has the potential to generate up to According to the ratio allocated to its DC sources, there are 17 output levels. Aside from increasing the number of output voltage levels, this study has a relatively low number of component counts. The THD limit defined by IEEE standard is also a goal (i.e. 5 percent) all voltage applications under 69kV.To ensure that the suggested topology is functional, it is being simulated in Matlab/Simulink with various modulation indexes. The amount of THD, the number of voltage outputs, and the RMS voltage are all being monitored and discussed. Finally, to assess the uniqueness of the suggested topology, a comparison study with recently disclosed topologies is being carried out.

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