The Study of the Various VLSI Design Method

Dharminder Kumar

doi:10.55524/

Authors

Dharminder Kumar Assistant Professor, Department of Electrical Engineering, RIMT University, Mandi Gobindgarh, Punjab, India Author

DOI:

https://doi.org/10.55524/

Keywords:

Dynamic Power, Leakage power, Very Large - Scale Integrated (VLSI), VLSI design

Abstract

VLSI outlooks for the Very Large Scale Integrated, and this is a very advanced electronic technology. VLSI circuits have been used in a variety of applications, including microcontrollers, microcomputers, n chips, chips used in a graphics processor, camcorders,

and video cameras. The notion of the "VLSI design approach" is discussed in this article, and research methodologies for VLSI design are provided using flow charts. The results of VLSI design, as well as the status of the methodologies and numerous infrastructures and designs associated with the VLSI design programme and approach, were also illustrated in this article. A network security branch, silicon implementation systems, a semiconductors section, and semiconductor foundries from throughout the world are all part of the VLSI architecture design. Since it is responsible for manufacturing processes and development such as transistor count, processing shrinkage, voltages scaling, timers gating, and fuzzy logic control, this research examines the newest growth and advances of low power VLSI. VLSI power loss is a well-known problem, according to the research, because this limited VLSI is in charge of the manufacturing implementation, including transistor size, process shrinkage, voltage scaling, clock gating, and so on. This study also aims to demonstrate and illustrate current and future trends in low-power VLSI research and innovation. In the realm of electronics, VLSI has a wide variety of applications.

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References

Sharma M, Gupta N, Gupta R. POWER REDUCTION TECHNIQUES IN VLSI. Int J Eng Technol Manag Res. 2020;

Soumya N, Sai Kumar K, Raghava Rao K, Rooban S, Sampath Kuma R P, Santhosh Kumar GN. 4-bit multiplier design using cmos gates in electric VLSI. Int J Recent Technol Eng. 2019;

Liu B, Qu G. VLSI supply chain security risks and mitigation techniques: A survey. Integr VLSI J. 2016; [4] Brown RB, Bernhardt B, LaMacchia M, Abrokwah J,

Parakh PN, Basso TD, et al. Overview of complementary GaAs technology for high-speed VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1998.

Kumar SBV, Rao P V., Sharath HA, Sachin BM, Ravi US, Monica B V. Review on VLSI design using optimization and self-adaptive particle swarm optimization. Journal of

King Saud University - Computer and Information Sciences. 2020.

Sub-threshold Design for Ultra Low-Power Systems. Sub threshold Design for Ultra Low-Power Systems. 2007. [7] Zhang Y. A foundation for the design and analysis of robotic

systems and behaviors. ProQuest Dissertations and Theses. 1994.

Venkatraman S, Sundhararajan M. Area and interconnect length optimization for VLSI floor planning problem by using harmony search algorithm. Int J Recent Technol Eng. 2019;

Tsunekawa Y, Hinosugi M, Miura M. Design and VLSI evaluation of a high-speed cellular array divider with a selection function. Electr Eng Japan (English Transl Denki Gakkai Ronbunshi). 1998;

Saab Y. New 2-way multi-level partitioning algorithm. VLSI Des. 2000;

Ignatyev V V., Kovalev A V., Spiridonov OB, Kureychik VM, Ignatyeva AS, Safronenkova IB. Hybrid genetic paired-permutation algorithm for improved VLSI placement. ETRI J. 2021;

Scalise F, Balanza M, Chauve N, Combelles P, Penard P, Del Toso C, et al. A prototype VLSI solution for digital terrestrial TV receivers conforming to the DVB-T standard. SMPTE J. 1997;

Venkatraman S, Sundhararajan M. A metaheuristic algorithm for VLSI floorplanning problem. Int J Recent Technol Eng. 2019;

Scalise F, Balanza M, Chauve N, Combelles P, Penard P, Del Toso C, et al. A Prototype VLSI Solution for Digital Terrestrial TV Receivers Conforming to the DVB-T Standard. In: International Workshop on HDTV 1996. 2015.

Chen X, Liu G, Xiong N, Su Y, Chen G. A Survey of Swarm Intelligence Techniques in VLSI Routing Problems. IEEE Access. 2020;

Wolf M, Mukhopadhyay S. VLSI for the Internet of Things. Computer (Long Beach Calif). 2017;

Sravani MM, Ananiah Durai S. Attacks on cryptosystems implemented via VLSI: A review. J Inf Secur Appl. 2021; [18] Macii E, Pedram M, Somenzi F. High-level power modeling, estimation, and optimization. IEEE Trans Comput Des Integr Circuits Syst. 1998;

Sakemi Y, Morino K, Morie T, Aihara K. A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy Efficient VLSI Processor Design. IEEE Trans Neural Networks Learn Syst. 2021;

Hemaspaandra LA. SIGACT news complexity theory column 31. ACM SIGACT News. 2001;

Sathasivam S, Mamat M, Mansor MA, Kasihmuddin MSM. Hybrid discrete hopfield neural network based modified clonal selection algorithm for VLSI circuit verification. Pertanika J Sci Technol. 2020;

Dewan MI, Kim DH. NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization. IEEE Trans Comput Des Integr Circuits Syst. 2020;

Bartolozzi C, Indiveri G. Synaptic dynamics in analog VLSI. Neural Comput. 2007;

Sivakumar R, Jothi D. Recent Trends in Low Power VLSI Design. Int J Comput Electr Eng. 2014;6(6):509–23. [25] Elrabaa MS, Abu-Khater IS, Elmasry MI, Elrabaa MS, Abu Khater IS, Elmasry MI. Low-Power VLSI Design. In: Advanced Low-Power Digital Circuit Techniques. 1997.