2:1 Multiplexer Design Using Lector, LCnmos, LCpmos Power Reduction Techniques with 45nm, 90nm, 180nm CMOS Technology
DOI:
https://doi.org/10.55524/Keywords:
Multiplexer, CMOS technology, Lector technique, LCnmos technique and LCpmos techniqueAbstract
Today’s modern communication requires high data transmission rate and low power consumption. One of the most common concept of data transmission can be achieved by Multiplexers. The Multiplexers are the logic designs where data can be transmitted by n number of inputs over transmission path based on the selection line producing the single input. The application of Multipis more active in communications system. AlsoLow power consumption and high-speed result is the major concern for choosing the digital circuits [1,2]. Here we designed 2:1 Multiplexer using CMOS technology with 45nm, 90nm, 180nm. Since CMOS offers less power consumption, we can till reduce the power consumed by using power reduction techniques. In this paper we designed and compared the 2:1 Multiplexer using Lector, LCnmos and LCpmos power reduction techniques.
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Design and analysis of 2: 1 multiplexer circuit for high performance. Abirami, M. Arul Kumar, E. Abinaya and J. Sowmaya, "Design and analysis of 2: 1 multiplexer circuit for high performance", International Journal of Electrical and Electronics Engineers Vol., no. 7, Jan-June 2015
Design of multiplexer in multiple logic styles for low power VLSI. M. Padmaja and V. N. V. Satya Prakash, "Design of multiplexer in multiple logic styles for low power VLSI", International Journal of Computer Trends and Technology, vol. 3, no. 3, 2012.
Anugraha RV, Durga DS. Design and performance analysis of 2: 1 multiplexerusing multiple logic families at 180 nm technology. IEEE Int Conf On RecentTrends in Elect Inf Comm Tech (RTEICT) 2017:1849–53.
AGARWAL, A. et al. Leakage Power Analysis and Reduction for Nanoscale Circuits, IEEE Micro, Los Alamitos, v.26, n.2, p 68-80, Mar. 2006
N. Hanchate and N. Ranganathan,” Lector: A technique for leakage reduction in CMOS circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 12, no. 2, pp. 196-205, February 2004.
Farzan Fallah and MassoudPedram, "Standby and active leakage current control and minimization in CMOS VLSI circuits", IEICE, January 2005.
Milind Gautam and ShyamAkashe, "Transistor gating: reduction of leakage current and power in full subtractor circuit", IEEE Advance Computing Conference(IACC), pp. 1514-1518, February 2013
V. K. Sharma and M. Pattanaik, "VLSI scaling methods and low power CMOS buffer circuit", Journal of Semiconductors, vol. 34, pp. 095001, 2013.
R. Lorenzo and S. Chaudhury, "LCNT-an approach to minimize leakage power in CMOS integrated circuits", Microsystem Technologies, vol. 23, no. 9, pp. 4245- 4253, 2017.
N. Ekekwe and R. Etienne-Cummings, "Power dissipation sources and possible control techniques in ultra-deep submicron CMOS technologies", Microelectron. Journal, vol. 37, no. 851, 2006.
A. Rjoub and M. Al-Ajlouni, "Efficient multi-threshold voltage techniques for minimum leakage current in nanoscale technology", Int. J. Circuit Theory Appl., vol. 39, no. 1049, 2011.
Anand N, George Joseph and Suwin Sam Oommen, “Performance Analysis and Implementation of Clock gating techniques for Low power applications”, International Conference on Science, Engineering and Management Research (ICSEMR 2014) 978-1- 4799-7613-3/14/$31.00 ©2014 IEEE.
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