Verification of UART and I2C Protocols Using System Verilog
DOI:
https://doi.org/10.55524/ijircst.2023.11.2.11Keywords:
Verification, Protocols, UART, I2C, System VerilogAbstract
Design Verification in VLSI is the most important step in the product development process. It aims toconfirmthatthe system designedmeetswith the standards andrequirements of the system. Verification is the process ofchecking whether the designed system performs all the required functionality specified in the design by writing the test bench or verification environment that contains group ofclasses and modules which generates input stimulus to the system and the output from that design is compared with the expected output. A communication system has set of roles those are called protocols. UART is a serial communication protocol that is used when only two devices are needed to communicate and it uses peer to peer topology.I2C stands for InterIntegrated Circuit used for communication between master and slave in which more thanone slave devices or memory can be connected to a master device. System Verilog has been primarily used for the verification purposes in VLSI because it has the features of Hardware Description Languages such as Verilog and VHDL,C and C++ and functional coverage, assertion coverage, constrained randomization and supports OOPs concepts.
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